ITEM 1. BUSINESS
Overview
We design, develop, and market field programmable gate arrays (FPGAs) and programmable system chips (PSCs) and supporting products and services. FPGAs and PSCs are used by manufacturers of automotive, communications, computer, consumer, industrial, military and aerospace, and other electronic systems to differentiate their products and get them to market faster. We are the leading supplier of FPGAs based on Flash and antifuse technologies, a leading supplier of high-reliability FPGAs, and the first supplier to offer a truly programmable PSC. Our strategy is to offer innovative solutions to markets in which our technologies have a competitive advantage, including the PSC market and the value-based and system-critical FPGA markets. In support of our PSCs and FPGAs, we offer intellectual property (IP) products; design and development software; programming hardware; debugging tool kits and demonstration boards; system design, online prototyping, and programming services; and a Web-based Resource Center.
We shipped our first FPGAs in 1988 and thousands of our development tools are in the hands of customers, including BAE Systems (BAE); The Boeing Company (Boeing); Cisco Systems, Inc. (Cisco); GE Medical Systems; Hamilton Sundstrand; Hewlett-Packard Company (HP); Honeywell International Inc. (Honeywell); Intel Corporation (Intel); Jabil Circuit, Inc. (Jabil); Lockheed Martin Corporation (Lockheed Martin); Motorola, Inc. (Motorola); the National Aeronautics Space Administration (NASA); Nokia; Nortel Networks Corporation (Nortel); Northrop Grumman Corporation (Northrop Grumman); Raytheon Company (Raytheon); Rockwell Collins, Inc. and Rockwell Automation, Inc. (Rockwell); Samsung; Schlumberger Limited (Schlumberger); Siemens AG (Siemens); Space Systems/Loral (SS/L); Tellabs, Inc. (Tellabs); UTStarcom Incorporated (UTStarcom); and Varian Medical Systems, Inc. (Varian).
We have foundry relationships with Chartered Semiconductor Manufacturing Pte Ltd (Chartered) in Singapore; Infineon Technologies AG (Infineon) in Germany; Matsushita Electric Industrial Co., Ltd. (Matsushita) in Japan; United Microelectronics Corporation (UMC) in Taiwan; and Winbond Electronics Corp. (Winbond) in Taiwan. Wafers purchased from our suppliers are assembled, tested, marked, and inspected by Actel and/or our subcontractors before shipment to customers.
We market our products through a worldwide, multi-tiered sales and distribution network. In 2005, sales made through distributors accounted for 64% of our net revenues. Unique Technologies, Inc., a sales division of Memec Group Holdings Limited (Memec), was our sole distributor in North America during 2004 and accounted for 33% of our net revenues in 2004. During 2005, Avnet, Inc. (Avnet) acquired Memec, after which Avnet became our sole distributor in North America. Unique and Avnet accounted for 30% of our net revenues in 2005. Including Avnet and about 17 sales representative firms, our North American sales network has about 87 offices. In 2005, sales to customers outside of North America accounted for 44% of our net revenues. Including about 20 distributors and sales representative firms, our European, Pan-Asia, and Rest of World (ROW) sales network has about 90 offices.
During the first quarter of 2005, we repurchased 627,500 shares of our Common Stock for $9.8 million. On May 16, 2005, we announced the approval by our Board of Directors of authority to repurchase up to 1,000,000 additional shares of Common Stock under our stock repurchase program. We have remaining authority to repurchase 1,610,803 shares under the program.
On March 7, 2005, we announced jointly with ARM Limited (ARM) a partnership to provide an ARM7 family processor (the world’s most widely used 32-bit RISC processor) to our customer base for use in several of our FPGA families. This partnership led to the creation of our CoreMP7 IP core, which permits the “soft-core” implementation of an ARM7 family processor in FPGA logic gates. Our CoreMP7 IP core is the first soft-core FPGA version of the ARM7 family processor that can be leveraged across the full range of products from high-volume, value-based applications to lower-volume, high-reliability applications. The soft core ARM7 family processor is delivered to customers using security features available only in our ARM-enabled FPGAs.
On July 18, 2005, we announced the Actel Fusion technology, which brings true programmability to mixed-signal (analog and digital) applications. The Actel Fusion technology is the first to integrate mixed-signal capabilities with Flash memory and FPGA fabric in a monolithic integrated circuit (meaning that all circuit components are integrated on a single uniform piece of material). The Actel Fusion technology brings the benefits of programmable logic to application areas that had been served only by discrete analog components and mixed-signal application-specific integrated circuits (ASICs). When used in conjunction with our ARM7- or 8051-based processor IP cores, the Actel Fusion technology constitutes a complete PSC platform.
On January 10, 2006, we announced that our CoreMP7 IP core had been selected as “Product of the Year” by Electronic Products magazine and named to EDN magazine’s Hot 100 Products of 2005 list. Our Actel Fusion PSC was also named to the Hot 100 Products list. On February 2, 2006, we announced that the Actel Fusion PSC is a finalist in this year’s EDN Innovation Awards. On February 13, 2006, we announced that the Actel Fusion PSC was named the winner of the International Engineering Consortium’s DesignVision award in the category of Semiconductors and ICs. An industry panel sponsored by the IEC selected the Actel Fusion PSC based on multiple criteria, including innovation, uniqueness, market impact, and customer benefits.
We were incorporated in California in 1985. Our principal facilities and executive offices are located at 2061 Stierlin Court, Mountain View, California 94043-4655, and our telephone number at that address is (650) 318-4200. Our Web site is http://www.actel.com . We provide access free of charge through a link on our Web site to our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, and Current Reports on Form 8-K, as well as amendments to those reports, as soon as reasonably practicable after the reports are electronically filed with or furnished to the Securities and Exchange Commission (SEC). The Actel, Axcelerator, EPGA, FlashLock, FuseLock, Libero, ProASIC, ProASIC PLUS, and VariCore names and logos are registered trademarks of Actel. This Annual Report also includes unregistered trademarks of Actel as well as registered and unregistered trademarks of other companies.
Industry Background
The two major kinds of integrated circuits (ICs) used in electronic systems are analog and digital circuits, although “mixed signal” ICs have both. The three principal types of digital ICs are processor, memory, and logic circuits. Processors are used for control and computing tasks; memory devices are used to store program instructions and data; and logic devices are used to adapt these processing and storage capabilities to a specific application. Logic circuits are found in practically every electronic system.
The logic design of competing electronic systems is often a principal area of differentiation. Unlike the processor and memory markets, which are dominated by a relatively few standard designs, the logic market is highly fragmented and includes, among many other segments, low-capacity standard transistor-transistor logic circuits (TTLs) and custom-designed ASICs. TTLs are standard logic circuits that can be purchased “off the shelf” and interconnected on a printed circuit board (PCB) but they tend to limit system performance and increase system size and cost compared with logic functions integrated at the circuit (rather than the PCB) level. ASICs are designed and built for a specific application, providing electronic system manufacturers with the benefits of increased circuit integration: improved system performance, reduced system size, and lower system cost.
ASICs include conventional gate arrays, standard cells, and programmable logic devices (PLDs). Conventional gate arrays and standard cell circuits are customized to perform desired logical functions at the time the device is manufactured. Since they are “hard wired” at the wafer foundry by the use of photomasks, conventional gate arrays and standard cell circuits are subject to nonrecurring engineering (NRE) charges and the time-to-market risks associated with any development cycle involving a foundry. Typically, hard-wired ASICs are first delivered in production volumes months after the successful production of acceptable prototypes. In addition, hard-wired ASICs cannot be modified after they are manufactured, which subjects them to the risk of inventory obsolescence and constrains the system manufacturer’s ability to change the logic design. PLDs, on the other hand, are manufactured as standard devices and customized “in the field” by electronic system manufacturers using computer-aided engineering (CAE) design and programming systems. PLDs are being used by a growing number of electronic system manufacturers to increase product differentiation and manufacturing flexibility and speed time to market.
PLDs include simple PLDs, complex PLDs (CPLDs), and FPGAs. CPLDs and FPGAs have gained market share because they generally offer greater capacity, lower total cost per usable logic gate, and lower power consumption than TTLs and simple PLDs; and faster time to market and lower development costs and inventory risks than hard-wired ASICs. As photomask costs and NRE charges continue to rise, CPLDs and particularly FPGAs are becoming cost-effective alternatives to hard-wired ASICs at higher volumes. Even in high volumes, the time-to-market and manufacturing-flexibility benefits of CPLDs and FPGAs often outweigh their price premium over hard-wired ASICs of comparable capacity for many electronic system manufacturers.
Before a CPLD or FPGA can be programmed, there are various steps that must be accomplished by a designer using CAE design software. These steps include defining the function of the circuit, verifying the design, and laying out the circuit. Traditionally, logic functions were defined using schematic capture software, which permits the designer to essentially construct a circuit diagram on the computer. As CPLDs and FPGAs have increased in capacity, the time required to create schematic diagrams using schematic capture tools has often become unacceptably long, so designers have generally turned to hardware description languages (HDLs). HDLs permit the designer to describe the circuit functions at an abstract level and to verify the performance of logic functions at that level using a simulator. The HDL description of the desired CPLD or FPGA device can then be fed into synthesis software, which automatically converts the abstract description into a gate-level representation equivalent to that produced by schematic capture tools. After a gate-level representation of the logic function has been created and verified, it must be translated or “laid out” onto the generic logic modules of the CPLD or FPGA. This is achieved by placing the logic gates and routing their interconnections, a process referred to as “place and route.” After the layout of the device has been verified by timing simulation, the CPLD or FPGA can be programmed. Multiple suppliers of electronic design automation (EDA) tools provide software to accomplish the design entry, simulation, and synthesis tasks for CPLDs and FPGAs, but the “place and route” and programming software is generally developed and provided only by the CPLD or FPGA supplier.
Electronic system manufacturers program a CPLD or FPGA to perform the desired logical functions by using a device programmer to change the state of the device’s programming elements (such as antifuses or memory cells) through the application of an electrical signal. Programmers are typically available from both the PLD supplier and third parties, and programming services are often available from both the PLD supplier and its distributors. Most CPLDs are programmed with erasable programmable read only memories or other nonvolatile “floating gate” memory technologies. Many FPGAs are programmed with static random access memory (SRAM) technology. Our FPGAs use Flash and antifuse programming elements. After programming, the functionality and performance of the programmed CPLD or FPGA in the electronic system must be verified.
To a large extent, the characteristics of a CPLD or FPGA are dictated by the technology used to make the device programmable. CPLDs and FPGAs based on programming elements controlled by floating gates or SRAMs must be configured by a separate boot device, such as the nonvolatile serial programmable read-only memory (PROM) commonly used with SRAM FPGAs. Because these CPLDs and FPGAs must be booted-up, they are less reliable (in the sense of being more prone to generate system errors), less secure, not functional immediately on power-up, and require a separate boot device. In addition, SRAM FPGAs and CPLDs based on look-up tables tend to consume more power. FPGAs based on Flash and antifuse programming elements do not need to be booted-up, which makes them more reliable, more secure, “live-at-power-up” (LAPU), single-chip solutions, and they also tend to operate at lower power. These are all characteristics shared by hard-wired ASICs but not by CPLDs or SRAM FPGAs.
The technology used to make a CPLD or FPGA programmable also dictates whether the device is reprogrammable and whether it is volatile. CPLDs and FPGAs based on programming elements controlled by floating gates or SRAMs are reprogrammable but lose their circuit configuration in the absence of electrical power. FPGAs based on antifuse programming elements are one-time programmable and retain their circuit configuration permanently, even in the absence of power. FPGAs based on programming elements controlled by Flash memory are reprogrammable and nonvolatile, retaining their circuit configuration in the absence of power.
As photomask and NRE costs for hard-wired ASICs continue to rise, FPGAs are increasingly used as a cost-effective alternative to hard-wired ASICs for implementing complex design functions. With this increase in adoption, FPGAs have grown in size and complexity, making the security of the devices more important. More often than not, the key IP that differentiates an electronic system from competitive offerings is now implemented in programmable logic. Consequently, the vulnerability of each system’s unique value-added IP is often a direct function of the security capabilities of the system’s FPGA. Since SRAM-based FPGAs must be configured at power-on, the bitstream used to configure the SRAM FPGA can be intercepted in route at the circuit level, electronically “captured,” and replicated. Alternatively, this configuration data can be read from the configuration device and manipulated or copied, or the on-board PROM can be replicated. Flash and antifuse FPGAs do not require a start-up bitstream, eliminating the possibility of configuration data being intercepted.
SRAM FPGAs are also susceptible to being upset by neutrons and alpha particles. When SRAM memories are used for data storage, these neutron-induced errors are called “soft errors.” When SRAM memories are used to store the configuration of an FPGA, these neutron-induced errors are called “firm errors.” A firm error affects the device’s configuration, which may cause the device to malfunction. In addition, firm errors are not transient but will persist until detected and corrected. There is a significant and
growing risk of functional failure in SRAM-based FPGAs due to the corruption of configuration data. Historically a concern only for military, avionics, and space applications, firm errors have become more of a problem for ground-based applications with each manufacturing process generation. Radiation testing has shown that antifuse and Flash FPGAs are not subject to loss of configuration due to neutrons or alpha particles.
Electronic system manufacturers are continuing to demand greater flexibility, reliability, and performance as well as lower power, board space, and total system cost requirements. This has put increasing pressure on IC suppliers to integrate analog, processor, programmable logic, and nonvolatile memory circuits in a single chip. As a result, analog, processor, and hard-wired ASIC suppliers are moving to add configurability to their product lines, and PLD suppliers are moving to integrate analog, processor, and Flash memory into their products. In this race to develop PSC solutions, PLD suppliers have an advantage because programmable logic historically has been the most difficult of these technologies to master and the integration of analog and Flash memory has already been proven in processor and hard-wired ASIC technologies.
Strategy
Our Flash and antifuse technologies are different from, and have certain advantages over, the SRAM and other technologies used in competing PLDs. Our strategy is to offer innovative solutions to markets in which our technologies have a competitive advantage, including the PSC market and the value-based and system-critical FPGA markets.
A general competitive advantage that our technologies have is design security. Our nonvolatile, single-chip PSCs and FPGAs offer practically unbreakable design security. Decapping and stripping of our Flash devices reveals only the structure of the Flash cell, not the contents. Similarly, the antifuses that form the interconnections within our antifuse FPGAs do not leave a signature that can be electrically probed or visually inspected. In addition, special security fuses are hidden throughout the fabric of our Flash and antifuse devices. These FlashLock and FuseLock security fuses cannot be accessed or bypassed without destroying the rest of the device, rendering ineffective both invasive and noninvasive attacks.
l PSC Market
“System-on-a-chip” ICs (SoCs) contain all of the necessary hardware and electronic circuitry for a complete system and are increasingly used in small, complex electronic devices such as digital cameras, cellular phones, and personal digital assistants. We address this market with our Actel Fusion PSCs, which were introduced in 2005 and bring the benefits of true mixed-mode programmable logic to SoCs. By combining an advanced Flash FPGA core with Flash memory blocks and analog peripherals and using a fully functional on-chip soft Flash processor, the Actel Fusion devices allow designers to integrate a wide range of functionality into a single device, simplify system design, reduce total system cost, and upgrade during the production cycle or in the field. The Actel Fusion PSCs are the most comprehensive single-chip mixed-signal programmable logic solutions available today.
l Value-Based Market
Much of the logic market is driven by cost effectiveness. We address this value-based market, which we believe represents the fastest growing segment of the FPGA market, with our Actel Fusion, Flash, and ARM-enabled FPGAs. In addition to low cost, our FPGAs add the value of hard-wired ASICs to the benefits provided by other PLDs. Like other PLDs, our FPGAs reduce design risk, inventory investment, and time to market. Unlike other PLDs, our FPGAs are nonvolatile, LAPU, low-power, single-chip solutions. In addition, logic designers can choose to use either hard-wired ASIC or FPGA software tools and design methodologies, and
the architectures of our FPGAs enable the utilization of predefined IP cores, which can be reused across multiple designs or product versions. We also offer our customers a wide selection of cost-sensitive and small form-factor packages. During 2005, we introduced the Actel Fusion PSCs, which were designed specifically for system management and control applications; our ProASIC3 and ProASIC3E FPGA families, which are targeted specifically at the value-based FGPA market; and our ARM7-enabled M7 ProASIC3/E FPGAs, which make the ARM7 processor available to the masses without royalties or upfront licensing fees.
l System-Critical Market
The system-critical market is driven primarily by reliability and security. Much of the logic market for military and aerospace applications is driven by reliability, nonvolatility, security, and resistance to radiation effects. We address this market with our military, avionics, and space-grade FPGAs. Our antifuse and Flash FPGAs are reliable, nonvolatile, secure, and not susceptible to configuration corruption caused by radiation. During 2005, we shipped fully-qualified RTAX250S, RTAX1000S, and RTAX2000S FPGAs to customers developing space-flight systems and introduced the RTAX4000S FPGA, the highest density radiation-tolerant FPGA specifically designed for space applications. Much of the market for automotive applications is driven by cost as well as reliability, nonvolatility, and security. We address this market with our automotive line of FPGAs, which we believe is the PLD industry’s broadest automotive offering.
Products and Services
Our product line consists of:
4 mixed-signal Actel Fusion PSCs based on Flash technology,
4 reprogrammable FPGAs based on Flash technology,
4 one-time programmable FPGAs based on antifuse technology, and
4 high-reliability (HiRel) FPGAs.
In 2005, FPGAs accounted for 96% of our net revenues, most of which was derived from the sale of antifuse FPGAs. In support of our PSCs and FPGAs, we offer IP products; design and development software; programming hardware; debugging tool kits and demonstration boards; system design, online prototyping, and programming services; and a Web-based Resource Center.
l PSCs
On December 12, 2005, we announced the immediate availability of the Actel Fusion PSCs, the world’s first mixed-signal FPGA family. By integrating mixed-signal analog, Flash memory, and FPGA fabric in a monolithic PSC, the Actel Fusion devices enable designers to rapidly deliver feature-rich systems to market. In addition, when used in conjunction with our ARM7- or 8051-based soft processor cores, the Actel Fusion technology provides a complete PSC platform. On March 6, 2006, we announced an expanded design infrastructure in support of our M7AFS device, the ARM7-enabled version of the Actel Fusion PSC. Bridging the industry-standard ARM7 technology with the first mixed-signal FPGA family, the ARM7-enabled Actel Fusion PSC represents the “state-of-the-art” single-chip PSC platform. The M7AFS family includes four devices of varying gate densities, levels of embedded Flash, and analog channels. Samples of the M7AFS600 device are expected to be available in April 2006, with the M7AFS1500 scheduled for sampling in the second half of 2006.
Based on our ProASIC3/E FPGA architecture, the Actel Fusion PSCs take advantage of the unique properties of our Flash technology, including the ability to support high-voltage transistors, to meet the demanding requirements of mixed-signal system design. By integrating analog inputs and outputs (I/Os) and a configurable analog-to-digital converter, the Actel Fusion devices enable direct connection to and control of a wide variety of analog systems, including voltage, differential current, and temperature monitors. The embedded Flash memory gives electronic system designers exceptional flexibility, including the capability to reconfigure analog block settings to perform widely different functions by downloading data from embedded Flash memory. The Actel Fusion devices also feature FlashLock security fuses and industry-leading Advanced Encryption Standard (AES) decryption to secure programmed IP and configuration data; offer low-power sleep and stand-by modes for power-sensitive applications; and are specifically designed to handle Level 0 LAPU system supervisory activities (see “BUSINESS — Products and Services — Supporting Products and Services — Resource Center — LAPU”). The Actel Fusion PSCs are appropriate for power management, thermal management, power-up sequencing and configuration, battery charging, motor control, clock generation and distribution, and numerous other system management and control applications in the industrial, medical, military/aerospace, communications, consumer, automotive, and computer markets.
l FPGAs
FPGAs are used by manufacturers of automotive, communications, computer, consumer, industrial, military and aerospace, and other electronic systems to bring differentiated products to market rapidly. We are the leading supplier of FPGAs based on Flash and antifuse technologies.
To meet the diverse requirements of our customers, we offer all of our FPGAs (except the radiation-hardened devices) in a variety of speed grades, package types, and/or ambient (environmental) temperature tolerances. Commercial devices are qualified to operate at ambient temperatures ranging from zero degrees Celsius (0°C) to +70ºC. Industrial devices are qualified to operate at ambient temperatures ranging from -40°C to +85°C. Automotive devices are qualified to operate at ambient temperatures ranging from -40°C to +125ºC with junction temperatures up to 125ºC for Flash devices and up to 150°C for antifuse devices. Military devices are qualified to operate at ambient temperatures ranging from -55°C to +125ºC. “High-reliability” or “HiRel” devices are qualified to automotive or military temperature specifications. We are a leading supplier of high-reliability FPGAs.
The capacity of FPGAs is measured in “gates,” which traditionally meant four transistors. As FPGAs grew larger and more complex, no standard technique emerged for counting FPGA gates. The appearance of FPGAs with memory further complicated matters because memory gates cannot be counted in the same way as logic gates. When we use “gate” or “gates” to describe the capacity of FPGAs, we mean “maximum system equivalent gates” unless otherwise indicated.
£ Flash FPGAs
Our Flash-based FPGAs include the ProASIC3, ProASIC3E, M7 ProASIC3/E, ProASIC PLUS, and ProASIC families. The combination of a fine-grained, single-chip ASIC-like architecture and nonvolatile Flash configuration memory makes our Flash-based FPGAs economical alternatives to ASICs for low- and medium-speed applications. Unlike other FPGAs available on the market today, which are either volatile or non-reprogrammable, our Flash devices are nonvolatile and reprogrammable.
¤ ProASIC3/E and M7 ProASIC3/E
On January 24, 2005, we announced the ProASIC3 and ProASIC3E families, our third generation of Flash-based FPGAs. The ProASIC3/E families were designed to address the market demand for full-featured, cost-effective FPGAs in consumer, automotive, and other price-sensitive applications. Ranging in density from 30,000 to 3,000,000 gates, the new ProASIC3/E families offer integrated secure in-system programmability (ISP) using AES encryption, 64-bit 66 MHz Peripheral Component Interconnect (PCI) performance, and the FPGA industry’s first on-chip user Flash memory. On August 16, 2005, we announced the immediate availability of a ProASIC3 starter kit and sampling of our 250,000-gate ProASIC3 FPGA. Available in both prototyping and low-cost evaluation versions, the starter kit permits designers to explore the ProASIC3/E families’ architectural features, including secure ISP. On January 11, 2006, we announced that we had begun shipping our largest ProASIC3 device, the 1,000,000-gate A3P1000. On February 21, 2006, we announced the commercial qualification of ProASIC3 devices and M7 ProASIC3 devices, which enable the use of CoreMP7, our royalty- and license-free soft ARM7 processor core.
When fully introduced, the ProASIC3 family will consist of seven devices: the 30,000-gate A3P030; the 60,000-gate A3P060; the 125,000-gate A3P125; the 250,000-gate A30250; the 400,000-gate A3P400; the 600,000-gate A3P600; and the 1,000,000-gate A3P1000. The ProASIC3E family will consist of three devices: the 600,000-gate A3PE600; the 1,500,000-gate A3PE1500; and the 3,000,000-gate A3PE3000. We market the ProASIC3/E families as the world’s lowest cost FPGAs. The M7 ProASIC3/E family will consist of seven devices: the 250,000-gate M7A3P250; the 400,000-gate M7A3P400; the 600,000-gate M7A3P600 and M7A3PE600; the 1,000,000-gate M7A3P1000; the 1,500,000-gate M7A3PE1500; and the 3,000,000-gate M7A3PE3000. Our ARM7-enabled M7 ProASIC3/E FPGAs enable use of the ARM7 processor without royalties or upfront licensing fees. The ProASIC3/E and M7 ProASIC3/E FPGAs eliminate the need for various components on the system board, which reduces board space, increases reliability, simplifies inventory management, and lowers total system costs (see “BUSINESS — Products and Services — Supporting Products and Services — Resource Center — Total System Cost”).
¤ ProASIC PLUS
The ProASIC PLUS family of FPGAs, which was first shipped for revenue in 2002, consists of seven devices: the 75,000-gate APA075; the 150,000-gate APA150; the 300,000-gate APA300; the 450,000-gate APA450; the 600,000-gate APA600; the 750,000-gate APA750; and the 1,000,000-gate APA1000. As our second-generation Flash family, ProASIC PLUS devices offer added features and improved user-configurable I/Os and ISP compared with the first-generation ProASIC family. Manufactured on a 0.22-micron process at UMC, the ProASIC PLUS family can be ordered in approximately 266 speed, package, and temperature variations.
¤ ProASIC
The ProASIC family of FPGAs, which was first shipped for revenue in 1999, consists of four products: the 100,000-gate A500K050; the 290,000-gate A500K130; the 370,000-gate A500K180; and the 475,000-gate A500K270. Manufactured on a 0.25-micron embedded Flash process at Infineon, the family can be ordered in approximately 60 speed, package, and temperature variations.
£ Antifuse FPGAs
Our antifuse-based FPGAs include the Axcelerator, eX, SX-A, SX, MX, and legacy families, all of which are nonvolatile, secure, reliable, LAPU, single-chip solutions. Our antifuse FPGA devices span six process generations, with each new generation offering higher performance, lower power consumption, and improved economies of scale.
¤ Axcelerator
The Axcelerator family of FPGAs, which was first shipped for revenue in 2002, consists of five devices: the 125,000-gate AX125; the 250,000-gate AX250; the 500,000-gate AX500; the 1,000,000-gate AX1000; and the 2,000,000-gate AX2000. Manufactured on a 0.15-micron, seven-layer metal process at UMC, the family can be ordered in approximately 260 speed, package, and temperature variations. The Axcelerator family was targeted at high-speed communications and bridging applications and designed to deliver high performance, logic utilization, and design security with low power consumption.
¤ eX
The eX family of FPGAs, which was first shipped for revenue in 2001, consists of three devices: the 3,000-gate eX64; the 6,000-gate eX128; and the 12,000-gate eX256. Manufactured on a 0.25-micron antifuse process at UMC, the family can be ordered in approximately 132 speed, package, and temperature variations. The eX family was designed for the e-appliance market of internet-related consumer electronics and includes a sleep mode to conserve battery power. eX devices also provide a small form factor, high design security, and an undemanding design process. We market the eX family as a high-performance single-chip programmable replacements for low-capacity ASICs.
¤ SX-A and SX
The SX-A family of FPGAs, which was first shipped for revenue in 1999, consists of four products: the 12,000-gate A54SX08A; the 24,000-gate A54SX16A; the 48,000-gate A54SX32A; and the 108,000-gate A54SX72A. Manufactured on a 0.22-micron antifuse process at UMC and on a 0.25-micron antifuse process at Matsushita, the family can be ordered in approximately 407 speed, package, and temperature variations.
The SX family of FPGAs, which was first shipped for revenue in 1998, consists of four products: the 12,000-gate A54SX08; the 24,000-gate A54SX16 and A54SX16P; and the 48,000-gate A54SX32. Manufactured on a 0.35-micron antifuse process at Chartered, the family can be ordered in approximately 364 speed, package, and temperature variations.
SX was the first family to be built on our fine-grained, “sea of modules” metal-to-metal architecture. We market the SX-A and SX families as programmable devices with ASIC-like speed, power consumption, and pricing in volume production. In addition, the SX-A family offers I/O capabilities that provide full support for “hot-swapping.” Hot swapping allows system boards to be exchanged while systems are running, a capability important to many portable, consumer, networking, telecommunication, and fault-tolerant computing applications.
¤ MX
The MX family of FPGAs, which was first shipped for revenue in 1997, consists of six products: the 3,000-gate A40MX02; the 6,000-gate A40MX04; the 14,000-gate A42MX09; the 24,000-gate A42MX16; the 36,000-gate A42MX24; and the 54,000-gate A42MX36. Manufactured on 0.45-micron antifuse processes at Chartered and Winbond, the family can be ordered in approximately 658 speed, package, and temperature variations. We market the MX family as a line of low-cost, single-chip, mixed-voltage programmable ASICs for 5.0-volt applications.
¤ Legacy Products
The MX family incorporates the best features of our legacy FPGAs and over time should replace those earlier products in new 5.0-volt commercial designs. Legacy products include the DX, XL, ACT 3, ACT 2, and ACT 1 families.
¡ DX and XL
The 3200DX family of FPGAs, which was first shipped for revenue in 1995, consists of five products: the 12,000-gate A3265DX; the 20,000-gate A32100DX; the 24,000-gate A32140DX; the 36,000-gate A32200DX; and the 52,000-gate A32300DX. Manufactured on a 0.6-micron antifuse process at Chartered, the family can be ordered in approximately 298 speed, package, and temperature variations.
The 1200XL family of FPGAs, which was first shipped for revenue in 1995, consists of three products: the 6,000-gate A1225XL; the 9,000-gate A1240XL; and the 16,000-gate A1280XL. Manufactured on a 0.6-micron antifuse process at Chartered, the family can be ordered in approximately 247 speed, package, and temperature variations.
The DX and XL families were designed to integrate system logic previously implemented in multiple programmable logic circuits. The DX family also offers fast dual-port SRAM, which is typically used for high-speed buffering.
¡ ACT 3
The ACT 3 family of FPGAs, which was first shipped for revenue in 1993, consists of five products: the 3,000-gate A1415; the 6,000-gate A1425; the 9,000-gate A1440; the 11,000-gate A1460; and the 20,000-gate A14100. Manufactured on a 0.6-micron antifuse process at Chartered and a 0.8-micron antifuse process at Winbond, the family can be ordered in approximately 315 speed, package, and temperature variations. The family was designed for applications requiring high speed and a high number of I/Os.
¡ ACT 2
The ACT 2 family of FPGAs, which was first shipped for revenue in 1991, consists of three products: the 6,000-gate A1225; the 9,000-gate A1240; and the 16,000-gate A1280. Manufactured on 1.0- and 0.9-micron antifuse processes at Matsushita, the family can be ordered in approximately 126 speed, package, and temperature variations. ACT 2 was our second-generation FPGA family and featured a two-module architecture optimized for combinatorial and sequential logic designs.
¡ ACT 1
The ACT 1 family of FPGAs, which was first shipped for revenue in 1988, consists of two products: the 2,000-gate A1010 and the 4,000-gate A1020. Manufactured on 1.0- and 0.9-micron antifuse processes at Matsushita, the family can be ordered in approximately 172 speed, package, and temperature variations. ACT 1 was the original family of antifuse FPGAs.
£ HiRel FPGAs
Our HiRel FPGAs include automotive products, which are offered in plastic packages; military/avionics (Mil/Av) products, which are offered in plastic or ceramic (hermetic) packages; and radiation-tolerant (Rad Tolerant) and radiation-hardened (Rad Hard) products, which are offered in hermetic packages. We are a leading supplier of HiRel FPGAs and the leading supplier of Rad Tolerant and Rad Hard FPGAs. Our FPGAs have been designed into numerous military and aerospace applications, including command and data handling, attitude reference and control, communication payload, and scientific instrument interfaces. Our space-grade FPGAs have been on board more than 100 launches and accepted for flight-critical applications on more than 250 satellites.
On September 6, 2005, we revealed an extensive product roadmap that will enable military and aerospace engineers to develop system designs with greater reliability, features, and performance. As part of the roadmap, we intend to deliver the first flash-based LAPU FPGA for space applications, enabling reconfigurability during prototyping and in space. Our roadmap also included two additions to our antifuse-based families: the RTAX4000S device, which will be the industry’s highest-density radiation-tolerant FPGA at 4,000,000 gates; and the onshore-manufactured RHAX250S device, which will be radiation-hardened assured (RHA) and offer a guaranteed high total dose rating and Qualified Manufacturers Listing (QML) Class V screening. As part of our ongoing effort to support the military and aerospace markets, we will continue to develop military-temperature plastic (MTP), military-temperature hermetic (MTH), and MIL-STD-883 Class B (Class B) versions of our commercial products. Our general philosophy is to develop and deliver products to our commercial customer base and then enhance those products for our military and aerospace customers. However, with the benefit of funding from the United States Government (which we believe will be in the range of $2 to $3 million for 2006), we are attempting to develop by design a radiation-hardened version of our fourth-generation Flash-based FPGA architecture concurrently with the development of the commercial version.
On November 1, 2005, we held our first annual Actel Space Forum (ASF) in Los Angeles, followed on January 17, 2006, by ASF East in Beltsville, Maryland. These one-day events, organized exclusively for our global space customers, consisted of detailed technical presentations from Actel
and our partners, including First Silicon Solutions (FS2), Magma Design Automation, Inc. (Magma), Mentor Graphics Corporation (Mentor Graphics), and Synplicity, Inc. (Synplicity). The ASF forum provides designers of space systems with a user-group environment focused on a range of topics relevant to the space industry, including testing and qualification, user case studies, software trends, advanced packaging technology, and IP cores designed for space. Attendees also received a status update on the quality and reliability of our space-grade FPGAs (see the Risk Factors set forth in Item 1A of this Annual Report on Form 10-K for more information) as well as further details regarding our product roadmap. We plan to hold a European version of the ASF during the first half of 2006.
¤ Automotive
To address the rapidly growing and cost-sensitive automotive electronics market, we introduced in 2003 an automotive line of FPGAs covering a wide range of densities, voltages, and features. We offer extended automotive temperature versions of all members of our antifuse-based eX, SX-A, and MX families and Flash-based ProASIC PLUS family. Our nonvolatile, single-chip automotive FPGAs are complemented by the industry’s broadest package portfolio certified to perform in automotive temperature environments. Since they are rugged and highly reliable in extended temperature applications, our automotive solutions are suitable for use under the hood as well as inside and around the perimeter of the passenger cabin. We market our automotive line as the FPGA industry’s broadest automotive product portfolio that addresses the unique needs of vehicle designers.
¤ Mil/Av
Our Mil/Av devices are offered in three packaging and screening options. MTP devices are offered in plastic packages and screened to military temperature specifications. MTH devices are offered in hermetic packages and screened to military temperature specifications. Class B devices are offered in hermetic packages and screened to MIL-STD-883 Class B specifications.
All members of our antifuse FPGAs families (except for the AX125 and the three eX devices) are offered in MTP packaging and screening. We have received complete QML certification for the full line of MTP antifuse FPGAs, which can be integrated into design applications that would otherwise require higher-cost ceramic-packaged devices. The QML plastic certification also permits customers to integrate commercial and military production without compromising quality or reliability.
We offer 22 devices in MTH or Class B packaging and screening: the 2,000-gate A1010B; the 4,000-gate A1020B; the 6,000-gate A1425A; the 9,000-gate A1240A; the 11,000-gate A1460A; the 16,000-gate A1280A and A1280XL; the 20,000-gate A14100A and A32100DX; the 24,000-gate A54SX16; the 36,000-gate A32200DX; the 48,000-gate A54SX32 and A54SX32A; the 54,000-gate A42MX36; the 108,000-gate A54SX72A; the 250,000-gate AX250; the 300,000-gate APA300; the 500,000-gate AX500; the 600,000-gate APA600; the 1,000,000-gate APA1000 and AX1000; and the 2,000,000-gate AX2000. Hermetic-packaged Mil/Av devices are appropriate for avionics, munitions, harsh industrial environments, and ground-based equipment in which radiation survivability is not critical.
On May 2, 2005, we announced price reductions of up to 50% for our ProASIC PLUS FPGAs in MTP packages. The new lower cost pricing structure benefits designers of avionics applications who require extreme temperature-grade FPGAs but do not need the more expensive MTH or Class B packages to meet design requirements. On December 6, 2005, we announced the availability of the first fully qualified MIL-STD-883B Flash-based FPGAs. Our reprogrammable, nonvolatile ProASIC PLUS FPGAs passed extensive testing at extreme conditions to qualify for use in high-reliability defense applications, such as military avionics and weapons systems.
¤ Rad Tolerant
Dedicated to providing FPGAs that meet the stringent radiation and quality requirements of space applications, we are the world’s leading supplier of Rad Tolerant and Rad Hard FPGAs. We continue our commitment to the space community with the RTSX-SU and RTAX-S FPGA families, which were designed specifically for space applications. The RTSX-SU and RTAX-S families are built on a foundation of hardened latches, eliminating the need for software-generated triple-module redundancy or other single-event upset mitigation techniques.
On July 5, 2005, we announced the shipment of fully qualified RTAX-S FPGAs to customers developing high-reliability space-flight systems. The RTAX-S family offers sufficient density, performance, radiation-resistance, and features to meet the requirements of many satellite bus and payload applications, permitting designers to take advantage of the flexibility of FPGAs and freeing them from the front-end cost and schedule constraints associated with radiation-hardened ASICs. On September 6, 2005, we announced the highest density radiation-tolerant FPGA for space designs. The RTAX4000S FPGA significantly expands the number of space applications requiring high gate counts that can be supported by our antifuse-based RTAX-S family, including data processing applications in communications, earth observation, and scientific satellites.
Our Rad Tolerant family of FPGAs consists of eleven products: the 4,000-gate RT1020; the 6,000-gate RT1425A; the 11,000-gate RT1460A; the 16,000-gate RT1280A; the 20,000-gate RT14100A; the 48,000-gate RT54SX32SU; the 108,000-gate RT54SX72SU; the 250,000-gate RTAX250S; the 1,000,000-gate RTAX1000S; the 2,000,000-gate RTAX2000S; and the 4,000,000-gate RTAX4000S. These Rad Tolerant FPGAs are offered with Class B or extended flow/space (Class E) qualification and total dose radiation test reports are provided on each segregated lot of devices. The RT54SX32SU device is also offered in a chip carrier land grid substrate that enables the assembly of tested and programmed FPGAs into multi-chip modules for space applications. During the second quarter of 2005, we informed customers that our RT1020 part had been discontinued and provided customers with a last-time opportunity to purchase such part, subject to availability.
Our Rad Tolerant FPGAs are designed to meet the logic requirements for all types of military, civilian, and commercial space applications, including satellites, launch vehicles, and deep-space probes. They provide cost-effective alternatives to radiation-hardened devices when radiation survivability is important but not essential. In addition, our Rad Tolerant devices have design- and pin-compatible commercial versions for prototyping.
¤ Rad Hard
The Rad Hard family of FPGAs, which was first shipped for revenue in 1996, consists of two products: the 4,000-gate RH1020 and the 16,000-gate RH1280. The two products were manufactured on a radiation-hardened 0.8-micron antifuse process by BAE and shipped with full QML Class V screening. The Rad Hard family was designed to meet the demands of applications requiring guaranteed levels of radiation survivability. Rad Hard FPGAs are appropriate for military and civilian satellites, deep space probes, planetary missions, and other applications in which radiation survivability is essential. During the second quarter of 2005, we informed customers that our RH1020 and RH1280 parts had been discontinued and provided customers with a last-time opportunity to purchase such parts, subject to availability.
During the third quarter of 2005, we announced plans to deliver the RHAX250S device, a 250,000-gate Rad Hard FPGA derived from our RTAX-S family that will be manufactured at BAE Systems’ Rad Hard CMOS foundry in Manassas, Virginia. The BAE Systems’ foundry will give the product two distinct benefits for space-flight customers. First, it will be an RHA product with a high guaranteed total dose rating and QML Class V screening. Second, it will be manufactured entirely within the continental United States, as required by the “trusted foundry” initiative recently established by the U.S. Department of Defense. No competitor today offers a Rad Hard FPGA of this density level from an onshore foundry. Products are planned for delivery by the end of 2006.
l Supporting Products and Services
In support of our PSCs and FPGAs, we offer IP products; design and development software; programming hardware; debugging tool kits and demonstration boards; system design, online prototyping, and volume programming services; and a Web-based Resource Center.
On December 12, 2005, we announced a comprehensive design environment that fully supports implementation of the new Actel Fusion PSC. The combination of the Actel Fusion PSC and the Actel Libero Integrated Design Environment (IDE) 7.0 enabled the convergence of digital logic, analog functionality, embedded Flash memory, and FPGA fabric on a single chip. Our Libero IDE allows full PSC generation in a “pick-and-click” user interface while a low-cost Actel Fusion starter kit permits a design to be taken from concept to completion. On January 17, 2006, we enhanced the Actel Fusion mixed-signal PSC offering with an ecosystem that supports power and thermal management applications. The Actel Fusion Ecosystem enables customers to speed the development and reduce the complexity of designs implemented on Actel Fusion PSCs.
£ IP Products
We supply IP cores, components, tools, and design services for standard functions, leaving the system designer free to focus on adding value to designs. Our IP products are optimized and verified for use with Actel devices, so designers can spend time developing and verifying the system instead of the IP components. We support the communications, consumer, military, industrial, automotive, and aerospace markets with more than 130 IP products designed and optimized to work with our devices.
Our DirectCore and CompanionCore IP cores enable system designers to streamline their design process, shorten time to market, and reduce design costs and risks. DirectCores are designed,
verified, supported, and maintained by Actel. They come complete as pre-implemented, synthesizable building blocks and have been thoroughly tested and verified in our devices. In addition, a number of them are certified for operation to a standard, such as PCI, the ARM7 architecture, or MIL-STD-1553. CompanionCores are sourced, verified, supported, and maintained by our IP partners. They are proven, pre-built IP cores optimized for use in our devices and tools. All Actel IP cores are compatible with our Libero IDE suite of development tools, and many are delivered other solution elements (such as documentation, development kits, design services, and support) that simplify integration. Additional IP cores, hardware and software components and tools, and design services are available from Actel Solution Partners.
On January 24, 2005, we announced the availability of more than 90 IP cores to support our new ProASIC3 and ProASIC3E FPGA families. Delivering a broad IP library at the time of product introduction allowed our customers to begin designing complete systems with the ProASIC3/E devices. On June 1, 2005, we introduced CorePCIF, our most versatile FPGA PCI core. On August 23, 2005, we introduced CoreFFT, an IP core generator that produces optimized fast Fourier transform cores for use with our Flash- and antifuse-based families of FPGAs. CoreFFT is designed for high-reliability applications requiring resistance to high temperature, firm-error immunity, and radiation tolerance, such as radar, ground, and air communications, acoustics, oil production, and medical signal processing.
On October 24, 2005, we announced the immediate availability of CoreMP7, a soft ARM7 family processor optimized for use in our FPGAs, bringing the flexibility and fast time-to-market of programmable logic to an industry-standard processor technology. Under our agreement with ARM, we are offering the 32-bit ARM7 family processor for use in our products free of license fees, greatly reducing the cost of entry and increasing designer access to SoC development with the ARM7 family. On October 24, 2005, we also announced CoreConsole, an IP Deployment Platform developed to simplify the construction of FPGA-based, system-level applications. The tool plays an important role in facilitating the development of Actel Fusion PSCs implementing CoreMP7.
£ Design and Development Software
Our Libero IDE is a comprehensive development software suite that provides our customers with all of the tools necessary for them to define, verify, and implement their designs in our devices. By combining our internally-developed tools with industry-standard products from Magma, Mentor Graphics, SynaptiCAD, Inc., and Synplicity, the Libero IDE provides “one-stop shopping” and a development environment that ensures tool compatibility and interoperability. For customers who want to use their own design and verification tools, our Designer software is available as a standalone interactive design implementation tool suite. It is compatible with the most popular design entry and verification packages, including those from Cadence Design Systems, Inc., Mentor Grahics, Synopsys, Inc. (Synopsys), and Synplicity. The Designer software includes all of the tools required for a complete physical design implementation system, including timing and power analysis tools. The Libero IDE and Designer software suites are available in Platinum and free Gold editions.
On January 24, 2005, we announced that our Libero version 6.1 IDE provided complete support for our new Flash-based ProASIC3 and ProASIC3E devices. On July 11, 2005, we introduced the Libero version 6.2 IDE, which included a new static timing analysis environment and enhanced synthesis capabilities from Synplicity and physical synthesis features from Magma. On November 2, 2005, we unveiled our Libero version 6.3 IDE, which provided a secure design flow from synthesis through implementation for integrating CoreMP7 into our ARM-enabled devices. The
enhanced software also supported our new RTAX4000S device, the highest density FPGA designed specifically for space applications. On February 21, 2006, we announced that our free Libero Gold version 7.0 SP1 IDE now provides support for all Actel devices, including the ARM7-enabled devices, of 1,000,000 gates or less. On March 6, 2006, we announced the availability of the Libero version 7.1 IDE, which includes design support for the M7AFS600 device, the first in the M7AFS family of ARM7-enabled Actel Fusion PSCs. The core generator tool within the Libero IDE enables designers to directly control and configure the analog peripherals of M7AFS devices.
£ Programming Hardware
Programmers execute instructions included in files obtained from the Designer tool suite to program our FPGAs. We offer Silicon Sculptor II and FlashPro programmers. All of our FPGAs can be programmed by the Silicon Sculptor II programmer. The Silicon Sculptor II programmer is a compact, single-device programmer designed to allow concurrent programming of multiple units from the same PC. The Silicon Sculptor II is manufactured for Actel by BP Microsystems, Inc. (BP Microsystems). The FlashPro device programmers provide ISP support for our Flash FPGAs. The ISP feature permits devices to be programmed after they are mounted on a PCB. All FlashPro programmers connect to the PC and permit multiple Flash devices to be programmed in a Joint Test Action Group (JTAG) chain. The FlashPro3 programmer supports Fusion, ProASIC3, and ProASIC3E; the FlashPro Lite programmer supports ProASIC PLUS devices only; and the FlashPro programmer supports both ProASIC PLUS and ProASIC devices. All FlashPro series programmers are manufactured for Actel by FS2. In addition to programmers, we offer programming adapter modules, which must be used with the Silicon Sculptor II programmer; surface-mount sockets, prototyping adapter boards, and prototyping mechanical packages, which make it easier to prototype designs using our antifuse FPGAs; and accessories.
£ Debugging Tool Kits and Demonstration Boards
Design diagnostics and debugging tool kits and accessories permit designers to improve productivity and reduce time to market by removing the guesswork typically associated with the process of system verification. Our antifuse FPGAs contain internal circuitry that provides built-in access to every node in a design, enabling real-time observation and analysis of a device’s internal logic nodes. Silicon Explorer II is an integrated verification and logic analysis tool kit for the PC that accesses the probe circuitry, enabling designers to complete the design verification process at their desks. In addition, FS2 offers a trace and debug tool that supports our Flash-based devices as well as our AX, SX, and MX antifuse-based FPGAs. This software product is especially well suited to debug our Flash devices because it can utilize the FlashPro programmers to access the JTAG interface.
Starter kits and evaluation boards and accessories permit users to evaluate particular products or applications. Our starter kits permit designers to assess an FPGA technology without spending the time or money needed to design a specialized evaluation board. On January 24, 2005, we announced a starter kit to support our new Flash-based ProASIC3 and ProASIC3E FPGA families. We also offer starter kits for our Fusion PSC and ProASIC PLUS and Axcelerator FPGA families. Each kit includes a device from the particular family and design and programming software (and, for Flash-based devices, a programming interface and associated programmer). On February 28, 2006, we announced the availability of a development kit for the CoreMP7 soft ARM7 processor core. The kit provides users with everything they need to evaluate and design FPGA-based SoC applications, including the CoreMP7 IP core, an Actel ARM7-enabled M7 ProASIC3 device, and FPGA development tools.
£ Services
With our acquisition of the Protocol Design Services Group from GateField Corporation (GateField) in August 1998, we became the first FPGA provider to offer system-level design expertise. The Design Services organization operates out of a secure facility located in Mt. Arlington, New Jersey, and is certified to handle government, military, and proprietary designs. The organization provides varying levels of design services to customers, including FPGA, ASIC, and system design; software development and implementation; and development of prototypes, first articles, and production units. The Protocol Design Services team has participated in the development of a wide range of applications, including optical networks, routers, cellular phones, digital cameras, embedded DSP systems, automotive electronics, navigation systems, compilers, custom processors, and avionics systems.
Our Online Protoyping Service is a free samples delivery program for Actel antifuse FPGAs. Intended to make it easy for designers to evaluate and prototype with no up-front investment, the program allows customers to request samples of programmed FPGAs through a Web-based interface. The program currently supports our Axcelerator, SX-A, eX and MX families.
We offer high-volume programming for all device and package types in our programming center, which is located at our factory in Mountain View, California. Our facility is ISO 9001:2000, PURE, QML, and STACK certified (see “BUSINESS — Manufacturing and Assembly). Volume programming charges are based on the type of device and quantity per order.
£ Resource Center
Our Web-based Resource Center is intended to provide information on a variety of industry-wide issues related to the continued displacement of hard-wired ASICs by PLDs. Targeted at FPGA and ASIC designers and system architects, the Web site includes technology tutorials, frequently-asked questions, market overviews, application notes, white papers, glossaries of industry terms, and links to relevant articles and third-party resources.
On August 2, 2005, we announced our new eZone virtual magazine, which provides in-depth information and updates on our new products, technologies, and partnerships. The e-magazine also includes links to whitepapers, application notes, and resource centers. The inaugural issue of eZone featured in-depth information on our new ProASIC3 family of FPGAs as well as our partnership with ARM and involvement with the Airbus A380 commercial airliner.
¤ Live at Power-Up (LAPU)
The LAPU Resource Center provides designers with information regarding power-up issues, including links to whitepapers, product information brochures, application notes, and other technical information. To help simplify the selection of LAPU devices, we created a new LAPU classification system to quantify the initialization capabilities of various semiconductor solutions. Our LAPU device classification system has three levels: live at power-up (Level 0), live after power-up (Level 1), and live after system initialization (Level 2). Level 0 LAPU devices are operational between power-on and power-up (the time at which the applied voltage has reached the lower limit of system voltage and is stable) and include Actel’s devices and other nonvolatile FPGAs and most CPLDs and hard-wired ASICs. Level 1 LAPU devices require a configuration download from internal memory but are operational before
system initialization and include flash-in-package SRAM FPGAs and some CPLDs. Level 2 LAPU devices are operational only after the initialization of system clocks, resets, interfaces, and memories and include most processors and SRAM-based FPGAs. Only Level 0 LAPU devices can assist in system start-up tasks, system configuration, and supervision during voltage ramp-up. On September 26, 2005, we released new results showing that our nonvolatile FPGAs offer up to 4,000 times better power-on response time than competing SRAM-based FPGAs.
¤ Power
The Power Resource Center provides design engineers with information about the power characteristics of FPGAs as well as tools to estimate and design for low-power applications. The four basic power components that need to be examined when evaluating the power consumption of different FPGA technologies are in-rush (or power-up) power, configuration power, static power, and dynamic power. The total system power requirements are a combination of all four of the power components. Unlike SRAM FPGAs, Flash and antifuse FPGAs have no power-up or configuration power components. SRAM-based FPGAs also consume significantly more static power than their Flash and antifuse counterparts. All FPGA technologies exhibit similar dynamic power performance. Of the three primary FPGA technologies, only Flash and antifuse have power characteristics similar to hard-wired ASICs.
¤ Packaging
The Packaging Resource Center contains technical package details, discussions on the latest environmental issues, related industry articles and links, and design implementation tools. This portal was created as the primary source for technical information about our FPGA packaging solutions, but also serves as an industry reference for IC packaging issues and topics that impact the FPGA design community. A major environmental issue is the use of lead and other harmful compounds in commercial and consumer electronic devices. We have offered “green” and lead-free packages for all of our FPGA product families since 2004. All of our green packages, which we define as being free of lead, halogenated compounds, and antimony oxides, are guaranteed to provide the same benefits and features as our standard packages. We have also taken the extra step of qualifying our green packages to operate at the same moisture-sensitivity level as our standard packages, providing designers with additional assurance that they can use our green packages without compromising performance or reliability.
¤ Soft/Firm Errors
Independent radiation testing has shown that FPGAs based on Flash and antifuse technologies are not subject to configuration upsets caused by high-energy neutrons naturally generated in the earth’s atmosphere. The testing also determined that SRAM-based FPGAs are vulnerable to neutron-induced configuration loss not only under high-altitude conditions, as traditionally believed, but also in ground-based applications. A neutron-induced error in an SRAM cell controlling the configuration of an SRAM-based FPGA could result in an unpredictable change in functionality in the FPGA. This is called a firm error and may cause the host system to malfunction. In ground-based applications where reliability is a concern (such as medical equipment, radar systems, telecommunications switches, and routers),
neutron-induced malfunctions could significantly reduce system availability. In airborne applications entrusted to FPGAs (such as aircraft engine controllers, flight computers, and weapons systems), the corruption of the system’s functionality resulting from a configuration firm error could have disastrous consequences.
On March 14, 2005, we announced that an independent study confirmed that our devices are resistant to the harmful effects caused by naturally occurring alpha particles. Alpha particles are a form of radiation commonly emitted from impurities in semiconductor packaging material. Our nonvolatile Flash- and antifuse-based FPGAs suffered no failures during the testing, but volatile SRAM-based FPGAs from Altera Corporation (Altera) and Xilinx Corporation (Xilinx) suffered a considerable number of alpha-induced configuration upsets, shedding further light on the risks posed by SRAM-based FPGAs for high-reliability applications in the commercial, military, and aerospace industries. The results of this independent study were published as an update to the report, “Radiation Results of SER [Soft-Error Rate] Test of Actel, Xilinx, and Altera FPGA Instances,” which is available in our Soft/Firm Errors Resource Center. This Web site also contains technology tutorials, white papers, a comprehensive glossary, and relevant links.
¤ Design Security
The purpose of our Design Security Resource Center is to provide semiconductor and design professionals with a database of information about security risks and the potential associated losses. The Web site contains technology tutorials, application notes, white papers, glossaries, and other information and links about design security, security countermeasures, affected systems, and solutions to defeat unfriendly attacks. Our solution is a range of nonvolatile single-chip devices that offer practically unbreakable design security. An important consideration for reprogrammable devices is the extent to which they can be safely configured in the field with ISP. The Actel Fusion and ProASIC3/E families provide a comprehensive solution for IP and programming security: Flash FPGAs are nonvolatile, LAPU, single-chip, and have nonvolatile memory on-chip, providing storage for keys and identifiers to control the secure ISP and serialization processes; the contents of the FPGA and memory can be secured independently through our FlashLock mechanism; advanced AES encryption is used to secure transmission of programming files; and Message Authentication Control is used to verify that programming information is not altered during transmission. Secure ISP protects users of Actel Fusion and ProASIC3/E parts from harm in the form of overbuilding, device IP/design theft, product tampering, and other acts of malicious intent.
¤ Total System Cost
Total cost of ownership can be divided into two categories: the direct costs of the bill of materials (BOM) and PCB area and the less direct associated costs, which can be substantial and are often overlooked. Nonvolatile Flash and antifuse FPGA solutions offer direct cost savings by eliminating the support devices required by volatile SRAM-based FPGAs. Since our devices do not require reloading when system power is restored, there is no need for a configuration PROM or power sequencing, brownout detection, reset controller, or clock generator devices in the PCB design. In addition to reducing direct costs by eliminating unnecessary parts from the BOM and PCB, our nonvolatile Flash and antifuse FPGAs lower associated total system costs by reducing design
complexity; increasing reliability; lowering total system power consumption; reducing thermal, noise, and electro-magnetic interference (EMI) management issues; and simplifying materials management.
Markets and Applications
FPGAs can be used in a broad range of applications across nearly all electronic system market segments. Most customers use FPGAs in low to medium volumes in the final production form of their products. Some high-volume electronic system manufacturers use FPGAs as a prototyping vehicle and convert production to lower-cost ASICs, while others with time-to-market constraints use FPGAs in the initial production and then convert to lower-cost ASICs. For electronic systems that have shortened product life cycles, system manufacturers are finding that the cost difference between hard-wired ASICs and FPGAs begins to shrink and that manufacturing flexibility becomes a more important element in the semiconductor decision process. In addition, the emergence of new chip interface standards puts a premium on flexibility, causing more high-volume electronic system manufacturers to retain FPGAs in volume production.
l Military and Aerospace
In 2005, military and aerospace applications accounted for an estimated 41% of our net revenues. Rigorous quality and reliability standards and the need for design security are the primary product characteristics of the military and aerospace market. Our FPGAs have high quality and reliability and are almost impossible to copy or reverse engineer, making them appropriate for many military and aerospace applications. We believe that we are the world’s leading supplier of military and aerospace PLDs. Our customers in the military and aerospace market include: BAE; Boeing; Hamilton Sundstrand; Honeywell; Lockheed Martin; NASA; Northrop Grumman; Raytheon; Rockwell; and SS/L.
Our antifuse FPGAs are especially well suited for space applications, due to the high radiation tolerance of the antifuse and our FPGA architecture. Thousands of our FPGAs have performed flight-critical functions aboard manned space vehicles, earth observation satellites, and deep-space probes, and our FPGAs often perform mission-critical functions on important scientific missions in space. We participate in programs administered by the Goddard, Johnson, and Marshall Space Flight Centers of NASA, including the Space Shuttle, International Space Station, and Hubble Space Telescope. We also participate in programs at California Institute of Technology’s Jet Propulsion Laboratory, including the Mars Pathfinder and the Mars Spirit and Opportunity Rovers. Our FPGAs can also be found in spacecraft launched by practically every civilian space agency around the world, including the European Space Agency and the Japanese National Space Development Agency.
On January 12, 2005, we announced that our Rad Tolerant and Rad Hard FPGAs continued to perform critical functions in the Mars Exploration Rovers, Spirit and Opportunity, both of which had surpassed the one-year mark of exploring the surface of Mars. Among other functions, our FPGAs played instrumental roles in the camera electronics on each rover, which provided spectacular images of the Martian surface. On March 21, 2005, we announced that TELDIX had selected our ProASIC PLUS FPGAs for use in common processor modules for the Eurofighter Typhoon, a swing-role combat aircraft co-developed by Germany, Italy, Spain, and the United Kingdom. TELDIX’s common processor module was developed for use in the attack computer, navigation computer, and other flight-critical multiprocessing equipment. On June 21, 2005, we announced that we had provided FPGAs and IP core modules for numerous of applications onboard the Airbus A380 commercial airliner, which had just successfully completed its maiden test flight. More than 700 of our ProASIC PLUS and SX-A FPGA devices were designed into the following applications: flight computers; engine control and monitoring; braking systems; safety warning systems; cabin air conditioning and
pressurization; and cockpit displays. In addition, our Core10/100 IP module, an Ethernet Media Access Controller, and a ProASIC PLUS FPGA were selected for use in a communications link for the A380.
l Industrial
In 2005, industrial control and instrumentation applications accounted for an estimated 31% of our net revenues. Industrial control and instrumentation applications often require complex electronic functions tailored to specific needs. FPGAs offer programmability and high density, making them attractive to this segment of the electronic equipment market. Our customers in the industrial market include: Dunlop Aerospace; GE Medical Systems; Hospira, Inc.; Jabil; REMEC Defense & Space, Inc.; Schlumberger; Siemens; Ultra Electronics; and Varian.
On February 22, 2005, we announced that our Flash-based ProASIC PLUS FPGAs were chosen by General Vision for use in the company’s CogniSight image recognition engine technology. CogniSight can be used to synthesize the color, shape, and texture of visual objects, learn these signatures with a set of parallel silicon neurons, and then recognize identical or similar objects to produce a response. This “generic image recognition” technology targets applications in medical imaging, remote sensing, factory automation, automated security/sentry, defense video tracking, image content mining, and human system interfacing. Our ProASIC PLUS devices were selected for the CogniSight “neural network” embedded processing engine. On April 11, 2005, we announced that our ProASIC PLUS FPGAs were chosen by Integen Technologies to implement the core of its cable modem design, which forms part of its Guest Room Integrated Delivery System product used by several leading hotel chains throughout North America. The product delivers IP-based services such as video-on-demand, high-speed Internet, and voice-over-IP telephony. On January 30, 2006, we announced that our ProASIC PLUS FPGAs had been selected for use within FAR Systems’ Multifunctional Vehicle Bus (MVB) and Wire Train Bus onboard railway communication products. FAR Systems, the European market leader in railway onboard communication systems, used our APA450 FPGA as the basis of its MVBCF chip, the industry’s most highly integrated MVB controller.
l Communications
In 2005, communications applications accounted for an estimated 21% of our net revenues. Increasingly complex equipment must frequently be designed to fit in the space occupied by previous product generations. In addition, the communications environment rewards short development times and early market entry. The high density, high performance, and low power consumption of our antifuse FPGAs make them suitable for use in high-speed communications equipment. The high capacity, low cost, low power consumption, and reprogrammability of our Flash FPGAs make them appropriate for use in other communications applications. Our customers in the communications market include: Cisco; McDATA Corp.; Matsushita; Motorola; Mykotronx; Nokia; Nortel; Pulse Communications, Inc.; Tellabs; and UTStarcom.
On January 10, 2005, we announced that UTStarcom, a leading global supplier of IP access networking solutions, had selected our antifuse-based SX-A FPGA as a controller on the processor control board of UTStarcom’s mSwitch and 3G products.
l Consumer and Computer
In 2005, consumer and computer applications accounted for an estimated 7% of our net revenues. The markets for consumer and computer products are characterized by short product life cycles and, like the communications market, place a premium on security and early market entry for new products. The high performance, low power consumption, and low cost of antifuse FPGAs make them appropriate for use in
products enabling the portability of the internet, or “e-appliances,” and other high-volume electronic systems targeted for consumers, including MP3 players, digital cable set-top boxes, DSL and cable modems, digital cameras, digital film, multimedia products, and smart-card readers. FPGAs reduce the time to market for computer systems and facilitate early completion of production models so that development of hardware and software can occur in parallel. Our customers in the consumer and computer markets include: Bally Technologies, Inc.; Heber Limited; HP; Instem Technologies Limited; Intel; Matrox; Matushita; RadiSys Corporation; Samsung; and WMS Gaming Inc.
l Automotive
Although revenues from our automotive product line were not significant in 2005, we believe that we have the PLD industry’s broadest automotive offering. Today’s automobiles contain miles of wiring, hundreds of ICs and a wide variety of other electronic content. Increasing sophistication under the hood has required a wide range of systems in the cab to help operators monitor performance and control a variety of diagnostic and telematic functions. In addition, manufacturers are striving to differentiate their products with a variety of complex digital systems for entertainment and networked information appliances. As a result, in-car electronics content is increasing at a rapid rate. Our automotive solutions enable designers to realize the time-to market advantages of programmable logic while providing a solution that can meet the rapidly evolving requirements of the automotive industry. Our automotive products are intended for in-cab telematics, infotainment, and body control functions as well as under-the-hood drive train control and safety systems. Typical applications include audio, video, multimedia, navigation, safety retention system management, engine diagnostic and monitoring systems, and emergency response consoles. Because all Actel devices are reliable, single-chip solutions, they are well suited for flexible point-to-point connections inside and around the perimeter of the passenger cabin and under the hood.
Sales and Distribution
We maintain a worldwide, multi-tiered selling organization that includes a direct sales force, independent sales representatives, and electronics distributors. Our North American sales force consists of 52 sales and administrative personnel and field application engineers (FAEs) operating from 14 offices located in major metropolitan areas. Direct sales personnel call on target accounts and support direct original equipment manufacturers (OEMs). Besides overseeing the activities of direct sales personnel, our sales managers also oversee the activities of 17 sales representative firms operating from 38 office locations. The sales representatives concentrate on selling to major industrial companies in North America. To service smaller, geographically dispersed accounts in North America, we have a distribution agreement with Avnet, which has 35 offices in North America and became our sole North American distributor during 2005.
We generate a significant portion of our revenues from international sales. Sales to European customers accounted for 27% of net revenues in 2005. Our European sales organization consists of 21 employees operating from five sales offices and ten distributors and sales representatives having 35 offices. Sales to Pan-Asia and other international customers accounted for 17% of net revenues in 2005. Our Pan Asia and ROW sales organization consists of 16 employees operating from four sales offices and ten distributors and sales representatives having 50 offices.
Sales made through distributors accounted for 64% of our net revenues in 2005. As is common in the semiconductor industry, we generally grant price protection to distributors. Under this policy, distributors are granted a credit upon a price reduction for the difference between their original purchase price for products in inventory and the reduced price. From time to time, distributors are also granted credit on an individual basis for approved price reductions on specific transactions to meet competition. We also generally grant
distributors limited rights to return products. Because of our price protection and return policies, we generally do not recognize revenue on products sold to distributors until the products are resold.
Our sales cycle for the initial sale of a design system is generally lengthy and often requires the ongoing participation of sales, engineering, and managerial personnel. After a sales representative or distributor evaluates a customer’s logic design requirements and determines if there is an application suitable for our FPGAs, the next step typically is a visit to the qualified customer by a regional sales manager or an FAE from Actel or one of our distributors or sales representatives. The sales manager or FAE may then determine that additional analysis is required by engineers based at our headquarters.
Backlog
Our backlog was $42.6 million at January 1, 2006, compared with $41.2 million at January 2, 2005. We include in our backlog all OEM orders scheduled for delivery over the next nine months and all distributor orders scheduled for delivery over the next six months. We sell standard products that may be shipped from inventory within a short time after receipt of an order. Our business, and to a great extent that of the entire semiconductor industry, is characterized by short-term order and shipment schedules rather than volume purchase contracts. In accordance with industry practice, our backlog generally may be cancelled or rescheduled by the customer on short notice without significant penalty. As a result, our backlog may not be indicative of actual sales and therefore should not be used as a measure of future revenues.
Customer Service and Support
We believe that premiere customer service and technical support are essential for success in the FPGA market. Our customer service organization emphasizes dependable, prompt, accurate responses to questions about product delivery and order status. Many of our customers regularly measure the most significant areas of customer service and technical support.
Our FAEs located in Canada, China, France, Germany, Hong Kong, Italy, Japan, Korea, Taiwan, the United Kingdom, and the United States provide technical support to customers worldwide. This network of experts is augmented by FAEs working for our sales representatives and distributors throughout the world. Customers in any stage of design may also obtain assistance from our technical support hotline or online interactive automated technical support system. In addition, we offer technical seminars on our products, comprehensive training classes on our software, and functional failure analysis services.
We generally warrant that our FPGAs will be free from defects in material and workmanship for one year, and that our software will conform to published specifications for 90 days. To date, we have not experienced significant warranty returns.
Manufacturing and Assembly
Our strategy is to utilize third-party manufacturers for our wafer requirements, which permits us to allocate our resources to product design, development, and marketing. Our FPGAs in production are manufactured by:
4 Chartered in Singapore using 0.45- and 0.35-micron design rules;
4 Infineon in Germany using 0.25- and 0.13-micron design rules;
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Matsushita in Japan using 1.0-, 0.9-, 0.8-, and 0.25-micron design rules; | |
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UMC in Taiwan using 0.25/ 0.22- and 0.15-micron design rules; and | |
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Winbond in Taiwan using 0.8- and 0.45-micron design rules. |
Wafers purchased from our suppliers are assembled, tested, marked, and inspected by Actel and/or our subcontractors before shipment to customers. We assemble most of our plastic commercial products in China, Hong Kong, South Korea, and Singapore. Hermetic package assembly, which is often required for military applications, is performed at one or more subcontractor manufacturing facilities, some of which are in the United States.
On May 17, 2005, we announced a new packaging option for our FPGA devices designed to significantly reduce board size and weight in space-constrained military/aerospace applications. The hermetically sealed ceramic package has an extremely small footprint and is available for our RTSX32SU FPGAs, which are designed to function reliably under space-flight conditions, and for our A54SX32A FPGAs, which are suitable for a wide range of industrial and military applications. On July 7, 2005, we announced an expansion of our package selection to include a Land Grid Array option for our RTAX-S FPGA family. With this package, military and aerospace customers have the flexibility to use their proprietary or preferred-vendor technology to attach columns or solder balls to the package.
We are committed to continuous improvement in our products, processes, and systems and to making our quality and reliability systems conform to standards and requirements recognized worldwide. On May 18, 2005, we announced that we had received STACK certification from STACK International after an extensive audit verifying our commitment to delivering quality products. STACK International consists of major electronic equipment manufacturers serving the worldwide high-reliability and communications markets. We also announced that we had been recertified for ISO 9001:2000 after an audit by NSF International, a world leader in management systems registrations. These two certifications demonstrate the conformance of our quality systems to internationally recognized standards and are a benchmark of our commitment to supply high-quality FPGAs to our diverse customer base.
We are also QML and PURE certified. Our QML certification confirms that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the U.S. Department of Defense for monolithic ICs. QML certification demonstrates our commitment to supply the highest quality products for all types of high-reliability, military, and space applications. PURE, which stands for PEDs (plastic encapsulated devices) Used in Rugged Environments, is an association of European equipment makers dedicated to quality and reliability. Our PURE certification is for plastic quad flat pack packages.
Strategic Relationships
We enjoy ongoing strategic relationships with many of our customers, distributors, sales representatives, foundries, assembly houses, and other suppliers of goods and services, including the following:
On March 30, 2005, we announced jointly with Prover Technology, Inc. that the Prover eCheck equivalence checker had been validated for design verification in our Libero IDE and that Prover had joined our EDA Alliance Program. Prover eCheck provides designers with an automated solution to identify
implementation inconsistencies for our antifuse- and Flash-based FPGA devices in a range of high-reliability designs, including military, aerospace, and communications applications.
On July 26, 2005, we announced jointly with HDL Works the optimization of HDL Works’ EASE design entry tool for our Libero IDE design flow. The EASE Graphical HDL Design Entry environment provides for design entry, modification, and maintenance of VHDL, Verilog, and mixed-language designs for FPGAs and hard-wired ASICs. HDL Works also joined our EDA Alliance Program.
On January 24, 2006, we announced that BP Microsystems, a leader in the device programming business, had selected our Axcelerator FPGAs across BP’s full range of next-generation programming solutions. Further strengthening this partnership, all seventh-generation programmers from BP Microsystems will support our ProASIC3/E families of devices. The top-end robotic arm production programmers from BP Microsystems can program the ProASIC3/E devices in under 30 seconds, permitting the automatic programming of thousands of devices per day with little operator intervention. In addition, new jointly-developed programming software enables individual device serialization of the Flash read-only memory (ROM) in each ProASIC3/E FPGA.
Research and Development
Our research and development expenditures were $48.2 million, or 27% of net revenues, in 2005 compared with $45.4 million, or 27% of net revenues, in 2004 and $39.6 million, or 26% of net revenues, in 2003. Our research and development expenditures are divided among circuit design, software development, and process technology activities, all of which are involved in the development of new products based on existing or emerging technologies. In the areas of circuit design and process technology, our research and development activities also involve continuing efforts to reduce the cost and improve the performance of current products, including “shrinks” of the design rules under which such products are manufactured. Our software research and development activities include enhancing the functionality, usability, and availability of high-level CAE tools and IP cores in a complete and automated desktop design environment.
During 2005, we introduced our ground-breaking Actel Fusion mixed-signal PSCs (see “BUSINESS — Products and Services — PSCs), our leading-edge Flash and ARM-enabled Flash product families (see “BUSINESS — Products and Services — Flash FPGAs — ProASIC3/E and M7 ProASIC3/E), and our highest-density Rad Tolerant FPGAs for space designs (see “BUSINESS — Products and Services — HiRel FPGAs — Rad Tolerant). We also revealed our HiRel product roadmap, which includes a new onshore-manufactured Rad Hard FPGA with QML Class-V screening (see “BUSINESS — Products and Services — HiRel FPGAs). We are in the process of developing our fourth-generation Flash-based FPGA architecture (G4). While our general philosophy is to develop and deliver products to our commercial customer base and then enhance those products for military and aerospace customers, we are attempting (with the benefit of funding from the United States Government, which we believe will be in the range of $2 to $3 million for 2006) to develop by design a radiation-hardened version of G4 concurrently with the commercial development.
Competition
The FPGA market is highly competitive, and we expect that to increase as the market grows. Our competitors include suppliers of TTLs and ASICs, including conventional gate arrays and standard cells, simple PLDs, CPLDs, and FPGAs. Of these, we compete principally with suppliers of hard-wired ASICs, CPLDs, and FPGAs.
The primary advantages of hard-wired ASICs are high capacity, high density, high speed, and low cost in production volumes. These advantages are offset by long design cycles and high designs costs,
including photomask set and NRE charges. We compete with hard-wired ASIC suppliers by offering lower design costs (including low or no NREs), shorter design cycles, and reduced inventory risks. Some customers elect to design and prototype with our products and then convert to hard-wired ASICs to achieve lower costs for volume production. For this reason, we also face competition from companies that specialize in converting CPLDs and FPGAs, including our products, into hard-wired ASICs.
We also compete with suppliers of CPLDs. Suppliers of these devices include Altera, which purchased the PLD business of Intel in 1994; Lattice Semiconductor Corporation (Lattice), which purchased the CPLD businesses of Vantis Corporation in 1999; and Xilinx, which purchased the CPLD business of Philips Semiconductors in 1999. The circuit architecture of CPLDs gives them a performance advantage in certain lower capacity applications, although we believe that FPGAs generally compete favorably with CPLDs. However, Altera is significantly larger than Actel, offers broader product lines to a more extensive customer base, and has significantly greater financial, technical, sales, and other resources. In addition, many newer CPLDs are reprogrammable, which permits customers to reuse a circuit multiple times during the design process. While our Flash FPGAs are reprogrammable, antifuse FPGAs are one-time programmable, permanently retaining their programmed configuration.
We compete most directly with the other established FPGA suppliers: Xilinx, Altera, and Lattice, which purchased the FPGA business of Agere Systems, Inc. in 2002. We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999. While we believe our products and technologies are superior to those of Xilinx (as well as Altera and Lattice) in many applications requiring lower cost, nonvolatility, lower power, and/or greater security, Xilinx is substantially larger than Actel, offers a broader product line to a more extensive customer base, and has substantially greater financial, technical, sales, and other resources. In addition, the FPGAs of Xilinx, Altera, and Lattice are reprogrammable. While our Flash FPGAs are reprogrammable, antifuse FPGAs are one-time programmable.
Several companies have marketed antifuse-based FPGAs, including QuickLogic Corporation (QuickLogic). In 1995, we acquired the antifuse FPGA business of Texas Instruments Incorporated, which was the only second-source supplier of our products. Xilinx, which is a licensee of certain of our patents, introduced antifuse-based FPGAs in 1995 and abandoned its antifuse FPGA business in 1996. Cypress Semiconductor Corporation, which was a licensed second source of QuickLogic, sold its antifuse FPGA business to QuickLogic in 1997. We believe that we compete favorably with QuickLogic, which is also a licensee of certain of our patents.
To date, we are the only supplier of FPGAs with Flash-based architectures. In 1998, we entered into a strategic alliance with GateField under which we acquired the exclusive right to market and sell standard ProASIC products in process geometries of 0.35-micron and less. In 1999, we introduced the Flash-based ProASIC family of FGPAs. In 2000, we acquired GateField in a merger.
We believe that the important competitive factors in our market are price; performance; capacity (total number of usable gates); density (concentration of usable gates); ease of use and functionality of development tools; installed base of development tools; reprogrammability; strength of sales organization and channels; power consumption; reliability; security; adaptability of products to specific applications and IP; ease, speed, cost, and consistency of programming; length of research and development cycle (including migration to finer process geometries); number of I/Os; reliability; wafer fabrication and assembly capacity; availability of packages, adapters, sockets, programmers, and IP; technical service and support; and utilization of intellectual property laws. Our failure to compete successfully in any of these areas could have a materially adverse effect on our business, financial condition, or results of operations.
Patents and Licenses
As of March 10, 2006, we had 272 United States patents and applications pending for an additional 72 United States patents. We also had 65 foreign patents and applications pending for 57 patents outside the United States. Our patents cover circuit architectures, antifuse and Flash structures, and programming methods among other things, and expire between 2006 and 2023. We expect to continue filing patent applications as appropriate to protect our proprietary technologies. We believe that patents, along with such factors as innovation, technological expertise, and experienced personnel, will become increasingly important.
In connection with the settlement of patent litigation in 1993, we entered into a Patent Cross License Agreement with Xilinx, under which Xilinx was granted a license under certain of our patents that permits Xilinx to make and sell antifuse-based PLDs, and we were granted a license under certain Xilinx patents to make and sell SRAM-based PLDs. Xilinx introduced antifuse-based FPGAs in 1995 and abandoned its antifuse FPGA business in 1996. We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999.
In 1995, we entered into a License Agreement with BTR, Inc. (BTR) pursuant to which BTR licensed its proprietary technology to Actel for development and use in FPGAs and certain multichip modules. At the end of 2004, we elected under the License Agreement to convert to a non-exclusive license, as a consequence of which we will cease to pay BTR advance royalties after March 2006. We are engaged in an arbitration proceeding with BTR to determine whether certain Actel products are subject to ongoing royalties under the License Agreement.
In connection with the settlement of patent litigation in 1998, we entered into a Patent Cross License Agreement with QuickLogic that covers the products of both companies that were first offered for sale on or before September 4, 2000, or future generations of such products.
As is typical in the semiconductor industry, we have been and expect to be notified from time to time of claims that we may be infringing patents owned by others. When probable and reasonably estimable, we make provision for the estimated settlement costs of claims for alleged infringement. As we sometimes have in the past, we may obtain licenses under patents that we are alleged to infringe. While we believe that reasonable resolution will occur, there can be no assurance that these claims will be resolved or that the resolution of these claims will not have a materially adverse effect on our business, financial condition, or results of operations. Our failure to resolve a claim could result in litigation or arbitration, which can result in significant expense and divert the efforts of our technical and management personnel, whether or not determined in our favor. As discussed above, we are currently involved in an arbitration with BTR. In addition, our evaluation of the impact of these pending disputes could change based upon new information. Subject to the foregoing, we do not believe that the resolution of any pending patent dispute is likely to have a materially adverse effect on our financial position at January 1, 2006, or results of operations or cash flows for the fiscal quarter or year then ended.
Employees
At the end of 2005, we had 565 full-time employees, including 150 in marketing, sales, and customer support; 216 in engineering and research and development; 163 in operations; and 36 in administration and finance. This compares with 557 full-time employees at the end of 2004, an increase of 1%. Net revenues were approximately $317,000 per employee for 2005 compared with approximately $297,000 for 2004. This represents an increase of 7%. We have no employees represented by a labor union, have not experienced any work stoppages, and believe that our employee relations are satisfactory.
ITEM 1A. RISK FACTORS
Actel shareholders and prospective investors should carefully consider, along with the other information in this Annual Report on Form 10-K, the following:
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Our future revenues and operating results are likely to fluctuate and may fail to meet expectations, which could cause our stock price to decline, perhaps significantly. |
Our quarterly revenues and operating results are subject to fluctuations resulting from general economic conditions and a variety of risks specific to Actel or characteristic of the semiconductor industry, including booking and shipment uncertainties, supply problems, and price erosion. These and other factors make it difficult for us to accurately project quarterly revenues and operating results, which may fail to meet our expectations. Any failure to meet expectations could cause our stock price to decline significantly.
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A variety of booking and shipping uncertainties may cause our quarterly revenues and/or operating results to fall short of expectations. |
When we fall short of our quarterly revenue expectations, our operating results will probably also be adversely affected because the majority of our expenses are fixed and therefore do not vary with revenues.
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We derive a large percentage of our quarterly revenues from bookings received during the quarter, making quarterly revenues difficult to predict. |
Our backlog (which generally may be cancelled or deferred by customers on short notice without significant penalty) at the beginning of a quarter typically accounts for about half of our revenues during the quarter. This means that we generate about half of our quarterly revenues from orders received during the quarter and “turned” for shipment within the quarter, and that any shortfall in “turns” orders will have an immediate and adverse impact on quarterly revenues. There are many factors that can cause a shortfall in turns orders, including declines in general economic conditions or the businesses of our customers, excess inventory in the channel, and conversion of our products to hard-wired ASICs or other competing products for price or other reasons. In addition, we sometimes book a disproportionately large percentage of turns orders during the final weeks of the quarter. Any failure or delay in receiving expected turns orders would have an immediate and adverse impact on quarterly revenues.
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We derive a significant percentage of our quarterly revenues from shipments made in the final weeks of the quarter, making quarterly revenues difficult to predict. |
We sometimes ship a disproportionately large percentage of our quarterly revenues during the final weeks of the quarter, which makes it difficult to accurately project quarterly revenues. Any failure to effect scheduled shipments by the end of a quarter would have an immediate and adverse impact on quarterly revenues.
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Our military and aerospace shipments tend to be large and are subject to complex scheduling uncertainties, making quarterly revenues difficult to predict. |
Orders from the military and aerospace customers tend to be large and irregular, which contributes to fluctuations in our net revenues and gross margins. These sales are also subject to more extensive governmental regulations, including greater export restrictions. Historically, it has been difficult to predict if and when export licenses will be granted, if required. In addition, products for military and aerospace applications require processing and testing that is more lengthy and stringent than for commercial applications, which increases the complexity of scheduling and forecasting as well as the risk of failure. It is often impossible to determine before the end of processing and testing whether products intended for military or aerospace applications will fail and, if they do fail, it is generally not possible for replacements to be processed and tested in time for shipment during the same quarter. Any failure to effect scheduled shipments by the end of a quarter would have an immediate and adverse impact on quarterly revenues.
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We derive a majority of our quarterly revenues from products resold by our distributors, making quarterly revenues difficult to predict. |
We generate the majority of our quarterly revenues from sales made through distributors. Since we generally do not recognize revenue on the sale of a product to a distributor until the distributor resells the product, our quarterly revenues are dependent on, and subject to fluctuations in, shipments by our distributors. We are therefore highly dependent on the accuracy of shipment forecasts from our distributors in setting our expectations. We are also highly dependent on the timeliness and accuracy of resale reports from our distributors. Late or inaccurate resale reports, particularly in the last month of a quarter, contribute to our difficulty in predicting and reporting our quarterly revenues and/or operating results.
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An unanticipated shortage of products available for sale may cause our quarterly revenues and/or operating results to fall short of expectations. |
In a typical semiconductor manufacturing process, silicon wafers produced by a foundry are sorted and cut into individual die, which are then assembled into individual packages and tested. The manufacture, assembly, and testing of semiconductor products is highly complex and subject to a wide variety of risks, including defects in photomasks, impurities in the materials used, contaminants in the environment, and performance failures by personnel and equipment. In addition, we may not discover defects or other errors in new products until after we have commenced volume production. Semiconductor products intended for military and aerospace applications and new products, such as our Flash-based Actel Fusion PSCs and ProASIC 3/E FPGAs and antifuse-based Axcelerator FPGAs, are often more complex and more difficult to produce, increasing the risk of manufacturing- and design-related defects. Our failure to effect scheduled shipments by the end of a quarter due to unexpected supply constraints would have an immediate and adverse impact on quarterly revenues.
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Unanticipated increases, or the failure to achieve anticipated reductions, in the cost of our products may cause our quarterly operating results to fall short of expectations. |
As is also common in the semiconductor industry, our independent wafer suppliers from time to time experience lower than anticipated yields of usable die. Wafer yields can decline without warning and may take substantial time to analyze and correct, particularly for a company like Actel that utilizes independent facilities, almost all of which are offshore. Yield problems are most common at new foundries, particularly when new technologies are involved, or on new processes or new products, particularly new products on new processes. Our FPGAs are also manufactured using customized processing steps, which may increase the incidence of production yield problems as well as the amount of time needed to achieve satisfactory, sustainable wafer yields on new processes and new products. In addition, if we discover defects or other errors in a new product that require us to “re-spin” some or all of the product’s mask set, we must expense the photomasks that are replaced. This type of expense has become more significant as the cost and complexity of photomask sets has continued to increase. Lower than expected yields of usable die or other unanticipated increases in the cost of our products could reduce our gross margin, which would adversely affect our quarterly operating results. In addition, in order to win designs, we generally must price new products on the assumption that manufacturing cost reductions will be achieved, which often do not occur as soon as expected. The failure to achieve expected manufacturing or other cost reductions during a quarter could reduce our gross margin, which would adversely affect our quarterly operating results.
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Unanticipated reductions in the average selling prices of our products may cause our quarterly revenues and operating results to fall short of expectations. |
The semiconductor industry is characterized by intense price competition. The average selling price of a product typically declines significantly between introduction and maturity. We sometimes are required by competitive pressures to reduce the prices of our new products more quickly than cost reductions can be achieved. We also sometimes approve price reductions on specific sales for strategic or other reasons. Unanticipated declines in the average selling prices of our products could cause our quarterly revenues and/or gross margin to fall short of expectations, which would adversely affect our quarterly financial results.
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In preparing our financial statements, we make good faith estimates and judgments that may change or turn out to be erroneous. |
In preparing our financial statements in conformity with accounting principles generally accepted in the United States, we must make estimates and judgments that affect the reported amounts of assets, liabilities, revenues, and expenses and the related disclosure of contingent assets and liabilities. The most difficult estimates and subjective judgments that we make concern income taxes, inventories, legal matters and loss contingencies, and revenues. We base our estimates on historical experience and on various other assumptions that we believe to be reasonable under the circumstances, the results of which form the basis for making judgments about the carrying values of assets and liabilities that are not readily apparent from other sources. Actual results may differ materially from these estimates. In addition, if these estimates or their related assumptions change in the future, our operating results for the periods in which we revise our estimates or assumptions could be adversely and perhaps materially affected.
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Our gross margin may decline as we increasingly compete with hard-wired ASICs and serve the value-based market. |
The price we can charge for our products is constrained principally by our competition. While it has always been intense, we believe that price competition for new designs is increasing. This may be due in part to the transition toward high-level design methodologies. Designers can now wait until later in the design process before selecting a PLD or hard-wired ASIC and it is easier to convert between competing PLDs or between a PLD and a hard-wired ASIC. The increased price competition may also be due in part to the increasing penetration of PLDs into price-sensitive markets previously dominated by hard-wired ASICs. We have strategically targeted many of our products at the value-based market, which is defined primarily by low prices. If our strategy is successful, we will generate an increasingly greater percentage of our net revenues from low-price products, which may make it more difficult to maintain our gross margin at our historic levels. Any long-term decline in our gross margin may have an adverse effect on our operating results.
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We may not win sufficient designs, or the designs we win may not generate sufficient revenues, for us to maintain or expand our business. |
In order for us to sell an FPGA, our customer must incorporate our FPGA into the customer’s product in the design phase. We devote substantial resources, which we may not recover through product sales, to persuade potential customers to incorporate our FPGAs into new or updated products and to support their design efforts (including, among other things, providing design and development software). These efforts usually precede by many months (and often a year or more) the generation of FPGA sales, if any. In addition, the value of any design win depends in large part upon the ultimate success of our customer’s product in its market. Our failure to win sufficient designs, or the failure of the designs we win to generate sufficient revenues, could have a materially adverse effect on our business, financial condition, and/or operating results.
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Our products are complex and may contain errors or defects that could have a materially adverse effect on our business, financial condition, and operating results. |
Our products are complex and may contain errors, manufacturing defects, design defects, or otherwise fail to comply with our specifications, particularly when first introduced or as new versions are released. Our new products are being designed on ever more advanced processes, adding cost, complexity, and elements of experimentation to the development, particularly in the areas of mixed-voltage and mixed-signal design. We rely primarily on our in-house personnel to design test operations and procedures to detect any errors prior to delivery of our products to customers.
During 2003, several U.S. government contractors reported a small percentage of functional failures in our RTSX-S and SX-A antifuse devices manufactured on a 0.25 micron antifuse process at the original manufacturer of those FPGAs. On February 13, 2004, The Aerospace Corporation (Aerospace) proposed a series of experiments to test various hypotheses on the root cause of the failures and to generate reliability data that could be used by space industry participants in deciding whether or not to launch spacecraft with RTSX-S FPGAs that were already